1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Related Art
Most electronic devices include semiconductor devices. The semiconductor devices include electric elements such as transistors, resistors, and capacitors. The electric elements are designed to perform various functions and are integrated on a semiconductor substrate. For example, electronic devices such as computers or digital cameras include semiconductor devices such as a memory chip configured to store information, a processing chip configured to control the information, and the like. The memory chip and processing chip include electronic elements integrated on a semiconductor substrate.
Semiconductor devices need to be more highly integrated for good performance at lower prices to satisfy consumer demand. As the integration of the semiconductor device is increased, the design rule is reduced and patterns of the semiconductor device become miniaturized. As ultra-miniaturization and high integration of semiconductor devices has progressed, total chip area is increased in proportion to an increase in memory capacity. However, the area of a cell region, in which the patterns of the semiconductor device are formed, is actually reduced. Therefore, since many patterns have to be formed in the limited cell region to ensure the desired memory capacity, patterns with reduced critical dimensions (CD) are formed.
However, the development of exposure equipment for implementing fine patterns required for semiconductor devices is not keeping pace with other areas of semiconductor device development. For example, when a photoresist pattern containing silicon is formed by performing an exposure and developing process on a photoresist layer containing silicon using existing equipment, it is difficult to secure a fine photoresist pattern since the exposure equipment has a limited resolution.
Double patterning technology (DPT) is a method of forming fine patterns. DPT is classified into double exposure etch technology (DE2T), which exposes and etches two patterns having a pitch twice the final pattern pitch, and spacer patterning technology (SPT) using a spacer.
The spacer patterning technology is classified into positive spacer patterning technology and negative patterning technology. In general, the positive spacer patterning technology is applied to patterning of a 30 nm-graded semiconductor device.